Instruction Flow Amplifier: A Novel Architecture for In-Order Processor Front-End Optimization
DOI:
https://doi.org/10.64552/wipiec.v12i2.139Keywords:
Computer Architecture, RISC-V, ARM, Front-End, Gem5, In-Order Processor coresAbstract
This paper proposes the Instruction Flow Amplifier (IFA), a novel architecture designed to mitigate frontend bottlenecks in in-order processor cores. Using the Gem5 simulator, we evaluate Cycles Per Instruction (CPI), Instructions Per Cycle (IPC), branch prediction accuracy, and instruction cache misses to demonstrate front-end bottlenecks and quantify the performance gains achieved by the proposed architecture. Unlike traditional trace caches that primarily focus on instruction storage, the proposed IFA integrates a lightweight Dependency Analysis Unit (DAU) to enable pseudo-out-of-order dispatch within an energy-efficient in-order infrastructure. The experimental results demonstrate that the IFA acts as an effective instruction supply accelerator. In workloads dominated by tight loops (MatMult), the proposed architecture effectively saturates the pipeline, achieving a 28% IPC improvement. In control-heavy workloads (WikiSort), the IFA mitigates fetch latency through aggressive buffering, improving IPC by 13.4% with negligible impact on branch prediction accuracy.
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