An Efficient Hardware Implementation for CAVLC Encoder in H.264/AVC
Keywords:H.264/AVC, Entropy Encoding, CAVLC, FPGA
This paper presents an efficient FPGA implementation of the context-based adaptive variable length coding (CAVLC) in H.264/AVC. The proposed entropy encoder architecture includes three stages: scan stage, coding stage and bitstream packing. Its performance is optimized by eliminating or weakening data dependencies such as memory accessing and context based data, by computing codewords on-the-fly and by pipelining stages in the encoding process. The design has been synthetized and implemented on Kintex 7 FPGA board.