An Efficient Hardware Implementation for CAVLC Encoder in H.264/AVC

Authors

  • Milica Orlandić Department of Electronics and Telecommunications, Norwegian University of Science and Technology, NTNU

Keywords:

H.264/AVC, Entropy Encoding, CAVLC, FPGA

Abstract

This paper presents an efficient FPGA implementation of the context-based adaptive variable length coding (CAVLC) in H.264/AVC. The proposed entropy encoder architecture includes three stages: scan stage, coding stage and bitstream packing. Its performance is optimized by eliminating or weakening data dependencies such as memory accessing and context based data, by computing codewords on-the-fly and by pipelining stages in the encoding process. The design has been synthetized and implemented on Kintex 7 FPGA board.

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Published

2021-07-29

How to Cite

Orlandić, M. (2021). An Efficient Hardware Implementation for CAVLC Encoder in H.264/AVC. WiPiEC Journal - Works in Progress in Embedded Computing Journal, 2(1). Retrieved from https://wipiec.digitalheritage.me/index.php/wipiecjournal/article/view/12

Issue

Vol. 2 No. 1 (2016): WiPiEC Journal

Section

Articles

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