Culsans: An Efficient Snoop-based Coherency Unit for the CVA6 Open Source RISC-V application processor

Authors

  • Riccardo Tedeschi DEI, University of Bologna
  • Luca Valente DEI, University of Bologna
  • Gianmarco Ottavi DEI, University of Bologna
  • Enrico Zelioli IIS, ETH Zurich
  • Nils Wistoff IIS, ETH Zurich
  • Massimiliano Giacometti PlanV Tech
  • Abdul Basit Sajjad PlanV Tech
  • Luca Benini IIS, DEI, ETH Zurich, University of Bologna
  • Davide Rossi DEI, University of Bologna

Keywords:

cache coherency, RISC-V, tightly coupled, CVA6, Culsans, ACE

Abstract

Symmetric Multi-Processing (SMP) based on cache coherency is crucial for high-end embedded systems like automotive applications. RISC-V is gaining traction, and open-source hardware (OSH) platforms offer solutions to issues such as IP costs and vendor dependency. Existing multi-core cache-coherent RISC-V platforms are complex and not efficient for small embedded core clusters. We propose an open-source SystemVerilog implementation of a lightweight snoop-based cache-coherent cluster of Linux-capable CVA6 cores. Our design uses the MOESI protocol via the Arm’s AMBA ACE protocol. Evaluated with Splash-3 benchmarks, our solution shows up to 32.87% faster performance in a dual-core setup and an average improvement of 15.8% over OpenPiton. Synthesized using GF 22nm FDSOI technology, the Cache Coherency Unit occupies only 1.6% of the system area.

References

J. Balkind, M. McKeown, Y. Fu, T. Nguyen, Y. Zhou, A. Lavrov, M. Shahrad, A. Fuchs, S. Payne, X. Liang and others, "OpenPiton: An open source manycore research framework," ACM SIGPLAN Notices, vol. 51, p. 217–232, 2016.

P. Mantovani, D. Giri, G. Di Guglielmo, L. Piccolboni, J. Zuckerman, E. G. Cota, M. Petracca, C. Pilato and L. P. Carloni, "Agile SoC development with open ESP," in Proceedings of the 39th International Conference on Computer-Aided Design, 2020.

K. Asanovic, R. Avizienis, J. Bachrach, S. Beamer, D. Biancolin, C. Celio, H. Cook, D. Dabbelt, J. Hauser, A. Izraelevitz and others, "The rocket chip generator," EECS Department, University of California, Berkeley, Tech. Rep. UCB/EECS-2016-17, vol. 4, p. 6–2, 2016.

F. Zaruba and L. Benini, "The Cost of Application-Class Processing: Energy and Performance Analysis of a Linux-Ready 1.7-GHz 64-Bit RISC-V Core in 22-nm FDSOI Technology," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 27, pp. 2629-2640, November 2019.

A. Ottaviano, T. Benz, P. Scheffler and L. Benini, "Cheshire: A Lightweight, Linux-Capable RISC-V Host Platform for Domain-Specific Accelerator Plug-In," IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 70, pp. 3777-3781, 2023.

C. Sakalis, C. Leonardsson, S. Kaxiras and A. Ros, "Splash-3: A properly synchronized benchmark suite for contemporary research," in 2016 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), 2016.

J. Martins and S. Pinto, "Bao: A modern lightweight embedded hypervisor," in Proc. Embedded World Conf., 2020.

C. Fuguet, "HPDcache: Open-source high-performance L1 data cache for RISC-V cores," in Proceedings of the 20th ACM International Conference on Computing Frontiers, 2023.

C. Chen, X. Xiang, C. Liu, Y. Shang, R. Guo, D. Liu, Y. Lu, Z. Hao, J. Luo, Z. Chen, C. Li, Y. Pu, J. Meng, X. Yan, Y. Xie and X. Qi, "Xuantie-910: A Commercial Multi-Core 12-Stage Pipeline Out-of-Order 64-bit High Performance RISC-V Processor with Vector Extension : Industrial Product," in 2020 ACM/IEEE 47th Annual International Symposium on Computer Architecture (ISCA), 2020.

Downloads

Published

2024-08-20

How to Cite

Tedeschi, R., Valente, L., Ottavi, G., Zelioli, E., Wistoff, N., Giacometti, M., Basit Sajjad, A., Benini, L., & Rossi, D. (2024). Culsans: An Efficient Snoop-based Coherency Unit for the CVA6 Open Source RISC-V application processor. WiPiEC Journal - Works in Progress in Embedded Computing Journal, 10(2). Retrieved from https://wipiec.digitalheritage.me/index.php/wipiecjournal/article/view/64

Issue

Vol. 10 No. 2 (2024): WiPiEC Journal

Section

Articles

License

Copyright (c) 2024 Riccardo Tedeschi, Luca Valente, Gianmarco Ottavi, Enrico Zelioli, Nils Wistoff, Massimiliano Giacometti, Abdul Basit Sajjad, Luca Benini, Davide Rossi

Creative Commons License

This work is licensed under a Creative Commons Attribution-NonCommercial 4.0 International License.

License Terms: 

Except where otherwise noted, content on this website is lincesed under a  Creative Commons Attribution Non-Commercial License (CC BY NC) 

Use, distribution and reproduction in any medium, provided the original work is properly cited and is not used for commercial purposes, is permitted.

Copyright to any article published by WiPiEC retained by the author(s). Authors grant WiPiEC Journal a license to publish the article and identify itself as the original publisher. Authors also grant any third party the right to use the article freely as long as it is not used for commercial purposes and its original authors, citation details, and publisher are identified, in accordance with CC BY NC license. Fore more information on license terms, click here.