WiPiEC Journal - Works in Progress in Embedded Computing Journal

Autotuned Distribution of Multi-DNN Workloads on Multi-Accelerator SoCs

Federico Nicolás Peccia — 2026-08-25

Many machine learning applications require heterogeneous Deep Neural Networks (DNNs) to work collaboratively. Although several works have focused on how to serve these systems using cloud solutions, less attention has been paid to the edge scenarios. Particularly, coordinating heterogeneous AI workloads across a custom application-specific System-on-Chip (SoC) with multiple accelerators presents significant challenges. This work first demonstrates how to implement such a baseline system using a SoC generator framework, performs an ablation study prototyping different versions on an FPGA, details how an RTOS can be used to achieve model parallelism on multiple accelerators, and identifies gaps and limitations by executing a multi-DNN autonomous driving application. To improve the utilization of the system and increase throughput, we propose a method to distribute the execution of individual layers across accelerators. Instead of partitioning all layers in the same manner and statically allocating them at compile time, we select the ideal partitioning for each one during compilation using an autotuning process, and then dynamically assign them to the available accelerators during runtime. We analyze the variability in layer execution in a system with multiple accelerators and use this information to guide the runtime allocation of partitions. We demonstrate that our method achieves a mean 29 % and 40 % improvement in accelerator utilization and throughput over the model parallelism baseline, and a 10 % and 9 % improvement over a round-robin runtime distribution of partitions.

Clock-glitch Fault Characterization by Timing Comparison with Laser Fault Injection

Ludovic Claudepierre — 2026-08-25

Since clock-glitching and the voltage-glitching are nonlocalized techniques of fault injection, it is difficult to accurately characterize their fault effects. In contrast, laser fault injection is a localized technique in which the targeted element of the microprocessor is known. In this article, we present a method that exploits the advantages of laser fault injection to characterize the glitch fault effects. We first make an hypothesis about the physical location of the sensitive part that induces the fault by glitch injection. Then we compare the fault timing and execution timing for glitch and laser platforms. If the delay between the fault and the execution is the same for both platforms, the initial hypothesis is supported.

Dolunay: Architectural Support for Independent Thread Scheduling in a RISC-V SIMT Accelerator

Ahmet Zahit Can — 2026-08-25

Single-Instruction Multiple-Thread (SIMT) architectures have revolutionized data-parallel computing by providing a high-throughput abstraction that simplifies vector management. However, traditional stack-based SIMT models do not support intra-warp synchronization primitives such as mutexes and spin-locks. This work introduces Dolunay, a RISC-V-based Independent Thread Scheduling (ITS) SIMT accelerator. By only adding three custom instructions, Dolunay employs a cooperative multitasking model and explicit synchronization barriers at the hardware-level, and provides the forward-progress guarantees necessary to implement starvation-free algorithms. We evaluate Dolunay on the Cmod A7-35T FPGA module and demonstrate its ability to correctly execute kernels that deadlock on traditional stack-based architectures while still achieving parallel execution for conventional compute-heavy kernels.

Operation Count as a Performance Predictor: An Empirical Study of Lightweight AEAD Schemes

Raphaël Wintersdorff — 2026-08-25

This paper presents an analytical model for estimating the performance of cryptographic algorithms based on operation counting at the specification level. Aside from the requirement of having 32-bit operations available on the target, the proposed approach avoids platform-dependent assumptions by deriving a cost metric directly from the number of operations required by an algorithm description. This enables early-stage, target-independent performance comparison. The model is evaluated using the NIST lightweight cryptography competition benchmark results, where it is shown to accurately approximate cycle counts across a diverse set of algorithms. The results indicate that operation counting can provide a consistent relative ordering of computational cost, and even a good order of magnitude approximation, despite its simplicity compared to empirical measurement methods. In addition, the model is applied to algorithms protected against side-channel attacks using first-order Boolean masking schemes implemented with ISW gadgets. While the method has not yet been formally validated for masked implementations, it is used as an exploratory indicator of the additional overhead introduced by the masking countermeasure. Overall, this work suggests that specification-level operation counting can serve as a practical and low-cost tool for early performance estimation and comparative analysis of unprotected, and possibly masked cryptographic implementations.

Instruction Flow Amplifier: A Novel Architecture for In-Order Processor Front-End Optimization

João Antônio Temochko Andre — 2026-08-25

This paper proposes the Instruction Flow Amplifier (IFA), a novel architecture designed to mitigate frontend bottlenecks in in-order processor cores. Using the Gem5 simulator, we evaluate Cycles Per Instruction (CPI), Instructions Per Cycle (IPC), branch prediction accuracy, and instruction cache misses to demonstrate front-end bottlenecks and quantify the performance gains achieved by the proposed architecture. Unlike traditional trace caches that primarily focus on instruction storage, the proposed IFA integrates a lightweight Dependency Analysis Unit (DAU) to enable pseudo-out-of-order dispatch within an energy-efficient in-order infrastructure. The experimental results demonstrate that the IFA acts as an effective instruction supply accelerator. In workloads dominated by tight loops (MatMult), the proposed architecture effectively saturates the pipeline, achieving a 28% IPC improvement. In control-heavy workloads (WikiSort), the IFA mitigates fetch latency through aggressive buffering, improving IPC by 13.4% with negligible impact on branch prediction accuracy.

A Dual-Head Model for Host based Intrusion Detection on System-Call traces

Matthias Dippold — 2026-08-25

Host-based intrusion detection systems (HIDS) need to detect both unseen exploits from day one and recurring known attack families. Maintaining separate anomaly-detection and supervised-classification frameworks increases the computational and operational footprint — a cost that only a few embedded or edge devices can carry. To satisfy both requirements without increasing deployment overhead, we propose a single dual-head Convolutional Neural Network (CNN) operating over a sliding window of embedded system-call tokens. Head 1 is an autoregressive next-token prediction module that emits sequence-level anomaly scores derived from token-wise negative log-likelihood (NLL) estimates, while Head 2 is a supervised attack-classification module using a shared latent representation. The two heads jointly support concurrent anomaly detection and supervised attack classification within a single model.
The proposed framework is evaluated using the ADFA-LD Linux system-call benchmark [1]. The proposed framework achieves mean AUROC scores of 0.916 in the unsupervised setting and 0.979 in the supervised setting, outperforming the baselines reported in [2] under the reshuffled evaluation protocol in both settings. These results demonstrate that unified sequential representation learning can simultaneously support both zero-day anomaly detection and supervised attack classification refinement within a single operational HIDS framework, thereby reducing the operational complexity of practical HIDS deployments.

A Compiler-Aware Framework for Partitioned Neural Network Inference on FPGA DPUs

Federico Buccellato — 2026-08-25

The increasing adoption of Artificial Intelligence is driving the development of larger and more accurate neu-ral networks. However, their high computational cost leads to significant inference latency, especially on resource-constrained embedded platforms such as FPGA-based systems. To address this issue, AMD introduced the Deep Learning Processing Unit, an accelerator integrated into the Vitis AI toolchain for efficient execution of quantized neural networks. Nevertheless, models with many parameters can be difficult to deploy on a single board due to latency or capacity constraints. In these scenarios, splitting a model into separately compilable fragments becomes useful for more flexible deployment. This process is not immediate within the Vitis AI flow. Our analysis shows that manually partitioning a network into independently compiled sub-networks can remove compiler optimizations. In particular, losing the global view of the quantized XIR graph can prevent the toolchain from preserving DPU mapping, moving accelerable operations to the CPU and causing severe performance degradation. Based on this observation, we analyze the Vitis AI compiler and propose an XIR-level splitting framework that generates independently compilable .xmodel fragments while preserving the context required for DPU mapping. The approach keeps the workflow high-level, without requiring advanced hardware design expertise or low-level design changes. Experimental results on CNN and ConvViT-based models show that naive splitting can introduce slowdowns up to ×249 on CNNs and ×542 on ConvViT variants. The proposed framework restores correct DPU mapping by addressing boundary-context loss and incomplete dependency collection, bringing latency back to the expected range for hardware-accelerated execution.

An Exploratory Study on Code Smells Detection and Refactoring using LLMs

Giorgia Paisi — 2026-08-25

With the observed progress in machine learning (ML), and particularly the introduction of Large Language Models (LLMs), several activities related to code maintenance could be automated. That includes not only detection and evaluation of design flaws, but also code transformation and refactoring. However, the general-purpose LLMs, while being commonly used and popular, have not been specifically trained for code analysis, and may not be suitable for conducting software maintenance tasks due to biases, and inherent shortcomings of the models. In this paper, we explore if the widely available LLMs could aid the detection and the refactoring of code smells. We focus on four common smells (God Class, Long Method, Feature Envy, and Refused Bequest) and consider five prompts of diverse complexity, asking the model for detecting and removing the identified code smells. Results suggest that general-purpose LLMs cannot be reliably used for that. They can effectively detect or remove code smells only in simple cases, and frequently produce invalid code. However, their performance depends on various factors, e.g., the model, the specific code smell or the prompt objective and composition.

Microservice Decomposition using Many-Objective Optimization

Vadim Peczyński — 2026-08-25

The literature on Microservices Architecture (MSA) presents numerous approaches for decomposing systems into microservices with the goal of improving quality attributes such as scalability, maintainability, and elasticity. Studies indicate that practitioners typically consider multiple objectives simultaneously when defining service boundaries, making microservice decomposition an inherently multi-objective optimization problem. Within this context, evolutionary algorithms are well suited to exploring trade-offs among competing objectives. This work utilizes the Event Storming graph as the primary input for extracting domain entities and identifying their relationships. By combining semantic analysis of entity names with the structural information embedded in the Event Storming graph, candidate microservice decompositions are generated and optimized using the NSGA-III algorithm. The proposed approach seeks to improve the efficiency and accuracy of deriving microservice boundaries from Event Storming models while providing software architects and decision-makers with a systematic framework for analysing and evaluating decomposition alternatives.

Knowledge Retrieval Architectures for AI-Assisted Software Development: From Static Context to Autonomous Development Agents

Norbert Fijałek — 2026-08-25

The integration of Large Language Models (LLMs) into software development workflows has fundamentally transformed how developers interact with knowledge repositories, codebases, and documentation. However, traditional knowledge retrieval mechanisms face significant challenges when applied to the dynamic, multi-modal, and contextually-rich environment of software engineering. This survey provides a comprehensive analysis of knowledge retrieval architectures specifically designed for AI-assisted software development, examining the evolution from static context provision to autonomous development agents. Building upon this systematic examination, the paper delineates critical research directions that advance the theoretical and practical foundations of AI-assisted software development.

SIAM DSL: Accessible Structured Text for Bridging the Architecture-Impact Gap in Cyber-Physical Production Systems

Stefan Biffl — 2026-08-25

In semi-automated Cyber-Physical Production Systems (CPPSs) that use operator assistance systems, introducing product variants often induces severe hazards due to misaligned mental models between the assistance system, human operators, and actual production states. These discrepancies create highimpact deviations between the expected and actual runtime states of a production line. To prevent these socio-technical hazards, solution architects require early-stage elicitation of tacit domain knowledge regarding critical production paths and operator conditions. However, multi-domain modeling approaches remain largely inaccessible to production domain experts. To bridge this gap, we present the System Impact Architecture Model (SIAM) Domain-Specific Language (DSL), a lightweight, structured text language that integrates a System Architecture Model with a System Impact Model. The SIAM DSL provides a simple framework for capturing and comparing multi-domain Product-Process-
Resource (PPR) variations, facilitating forward and backward reasoning to identify risky production states. We explore the language’s efficacy through an illustrative case study of operator assistance design for gearbox assembly and derive a research agenda. The study results indicate that the SIAM DSL is effective for eliciting tacit dependencies and providing input to modeling
socio-technical assistance scenarios.

Large Language Models for Software Architecture Design Support in Self-Adaptive Systems: Early Insights from an Exploratory Systematic Review

Nadeem Abbas — 2026-08-25

Modern computing systems exhibit increasing heterogeneity and often require runtime self-management and adaptation to cope with their structural and operational complexity, as well as changes in their environment and requirements. Self-Adaptive Software Systems (SASS) represent a class of context-aware and autonomous systems designed to manage such complexity. However, designing such systems remains challenging due to their complexity, runtime variability, and the continuous need to ensure functional and quality requirements. Large Language Models (LLMs) and Generative AI (Gen AI) offer promising capabilities, yet their use in the architectural design of SASS remains poorly understood. To that end, this study reports a work in progress systematic review. The review findings reveal that the use of LLMs and other Gen AI approaches for the architectural design of SASS remains nascent, with only four relevant studies identified. Across these studies, LLMs act as augmentative reasoning components, concentrated in the monitoring, analysis, planning, and knowledge phases of the MAPE-K loop and are only partially present in execution. Characteristics such as hybrid architectures, multi-agent reasoning, and retrieval-augmented grounding recur across the reviewed studies; however, given the small and heterogeneous evidence base, these are best viewed as preliminary observations rather than established trends, and trustworthiness and runtime assurance remain underexplored. As a work in progress, this paper contributes an initial characterization of LLM-supported design in self-adaptive systems, outlines research directions, and aims to stimulate discussion within the community on advancing LLM-supported architectural design for self-adaptive and autonomous software systems.

Study of PicoTDC Performance for FIT Detector Upgrade in ALICE Experiment at CERN

Łukasz Drzensla — 2026-08-25

In this paper, we present the results of a study on the performance of the PicoTDC. PicoTDC is a new Time-to-Digital Converter (TDC) chip developed at CERN for time-of-flight measurements in high-energy physics experiments. Our research aimed to evaluate the feasibility of using the PicoTDC in the upgraded front-end electronics (FEE) of the Fast Interaction Trigger (FIT) detector in the ALICE experiment. The FIT detector provides the trigger signals for the other ALICE sub- detectors and operates under very tight latency constraints. Since the necessary PicoTDC performance data were not available in the published documentation, we decided to derive the required parameters from simulations. The unique contribution of this paper is a detailed explanation of the output signals’ timings of PicoTDC. Additionally, we propose a sensor channel allocation scheme that reduces the guaranteed PicoTDC processing time. We derive and present useful analytical formulas for calculating the output latency across different usage scenarios. Finally, we present a case study that assesses the feasibility and the conditions required to meet the latency and data-rate requirements when incorporating the PicoTDC into the upgraded FIT front-end electronics.

Design and Implementation of Three-stage RISC-V Microprocessor for Education

Jan Ber — 2026-08-25

In many computer science and embedded systems courses, processor architecture is typically introduced using either the classical five-stage RISC pipeline or the two-stage AVR pipeline. While these architectures provide a strong introduction to bare-metal programming and computer organization, they do not necessarily represent the most practical or accessible approach for teaching modern processor architectures. In particular, traditional five-stage pipelines often introduce considerable control and forwarding complexity, while compact microcontroller architectures may obscure fundamental pipeline behavior and instruction flow.
This paper presents X3S, a work-in-progress 32-bit pipelined RISC-V softprocessor core originally developed as author’s engineering thesis. The design adopts a simple three-stage pipeline intended to balance architectural clarity, implementation complexity, and achievable operating frequency on Field Programmable Gate Array (FPGA) devices. X3S implements the RV32I base integer instruction set together with the M extension for multiplication and division operations. Multi-cycle arithmetic
accelerators are integrated into the execution pipeline using a handshake-based interface.

A Low-Power ADC-Free Resistive Sensor Readout Circuit for μC-Based Microsystems

João Maia Aguiar — 2026-08-25

Implantable microsystems are required to show low-volume and low-power consumption, while ensuring high reliability and safe long‑term operation. This work addresses the development and evaluation of a compact readout circuit for a piezoresistive force sensor intended for integration in an active oral prosthesis. The approach proposed here can be included in the direct-to-microcontroller interface methodologies, but relies on a sigma-delta-like measurement process. Its performance has been experimentally compared to conventional Wheatstone bridge and simple voltage-divider topologies, showing, respectively, 76% and 44% reductions in power consumption, while ensuring 8 times better resolution.